Sigma SDC-RLV12 MA400250 REV C May 9, 1984 \ Contents SECTION 1 - GENERAL INFORMATION 1.1 INTRODUCTION 1 1.2 GENERAL DESCRIPTION 2 1.3 FEATURES 2 1.4 SPECIFICATIONS 3 SECTION 2 - INSTALLATION AND DIAGNOSTICS 2.1 INTRODUCTION 5 2.2 DEVICE ADDRESS SELECTION 7 2.3 DEVICE AND VECTOR ADDRESS SELECTION 8 2.4 INTERRUPT REQUEST LEVEL 9 2.5 DRIVE CONFIGURATION 9 2.5.1 Xebec and Adaptec Byte Format 13 2.5.2 OMTI Byte Format 14 2.5.3 lomega Byte Format 16 2.5.4 Drive Configuration PROM Examples 17 2.6 FORMATTER/CONTROLLER INSTALLATION 18 2.7 BOOTSTRAPPING AND 22-BIT ADDRESSING 20 2.8 OFF-LINE CONTROLLER FUNCTION 20 2.8.1 Drive Formatting 21 2.8.2 Writing Bad Sector File 22 2.8.3 Self-Test 22 2.9 DIAGNOSTIC COMPATIBILITY 26 SECTION 3 - PROGRAMMING CONSIDERATIONS 3.1 INTRODUCTION 27 3.2 CONTROL/STATUS REGISTER (CSR) 28 3.3 BUS ADDRESS REGISTER (BAR) 31 3.4 DISK ADDRESS REGISTER (DAR) 31 3.4.1 DAR during a Seek Command 32 3.4.2 DAR during Read, Write, or Write Check Command 33 3.5 MULTIPURPOSE REGISTER (MPR) 34 3.5.1 Writing the MPR to Set Word Count 34 3.5.2 Reading the MPR after a Read Header 35 3.5.3 Reading the MPR after'a Get Status 35 3.6 BUS ADDRESS EXTENSION REGISTER (BAE) 36 3.7 CSR COMMANDS 37 3.8 PROGRAMMING EXAMPLES 41 MA400250 REV C May 4, 1984 Page 3 1.4 SPECIFICATIONS Power Requirements: 5VDC at 2.5A typical. Priority Level: Selectable. Compatible with LSI-11/23 Device Address: 774400 standard. Selectable fixed alternate. Interrupt Vector: 160 (octal) standard. Selectable fixed alternate. Bus Load: Interface: SASI bus Media: Fixed Recording Method: Modified frequency modulation (MFM) Drives/controller: 2 (up to 4 logical units) Error Detection: Cyclic redundancy check (CRC) on data and headers. 11-bit ECC Cable: Requires 50-conductor ribbon cable to Xebec/ Adaptec/OMTI formatter or Alpha 10.5 drive (not included). Dimensions: Standard dual-wide module. 10.45" (26.6cm) high x 8.94" (22.7cm) wide. Installation: Plugs directly into any Q bus slot. Temperature Operating: O C to 50 C Storage: -16 C to 60 C Humidity: 10% to 95% noncondensing MA400250 REV C ______________ May 4, 1984 Page 6 | J1 | -------------------------------------- | 24 | | 25 | | 16 21 22 21 | | 17 18 19 20 | | | | | | | | | | 6 7 | | | | | | 28 29 12 13 | | 30 | | | | 8 9 | | 34 10 11 | | | | 33 | | 32 | | 31 1 2 | | | | 14 | | 15 | | | | | | 5 | | 27 26 4 3 | | | |_ _ _| |_______________| |________________| B A Mixed Capacity Drive Select 24 25 Test Only {34,16,17,12,13,5,4,3} Drive Type Select {21,22,23,18,19,20} (See Section- 2.5) Boot Enable Select 6-7 Extended Address 28 29 ODT Boot Enable 30 (See Section 2.7) Address {8,9,10,11,33,32,31} Interrupt Request Level (4 & 5) 1 2 Vector 14 15 MA400250 REV C May 4, 1984 Page 7 2.2 DEVICE ADDRESS SELECTION Software control of the SDC-RLVI2 is via five device registers with the following factory configured addresses: CSR Control Status Register 774400 BAR Bus Address Register 774402 DAR Drive Address Register 774404 MPR Multipurpose Register 774406 BAE Bus Address Extension Register 774410 The first four registers are used for 16- or 18-bit addressing. The bus address extension register (BAE) is included for upper address bit selection for 22-bit addressing. Three additional device registers are assigned by DEC at 774412, 774414, and 774416. These registers are unused by DEC; however, the SDC-RLVI2 uses 774414 to store error information from the S1410, and register 774416 to bootstrap from ODT. These functions are explained in more detail in later sections. The usual device starting address is listed in Table 2-1. The first register (CSR) is assigned the starting address, and the other registers are assigned the next sequential addresses as shown in Table 2-1. DEVICE 16-BIT 18-BIT 22-BIT ADDRESS ADDRESSING ADDRESSING ADDRESSING Starting Address Range 160000-177760 760000-777760 17760000-17777760 Starting Address 174400 774400 17774400 Registers CSR (174400) CSR (774400) CSR (17774400) Used BAR (174402) BAR (774402) BAR (17774402) DAR (174404) DAR (774404) DAR (17774404) MPR (174406) MPR (774406) MPR (17774406) BAE (17774410) TABLE 2-1: ADDRESS SELECTION The SDC-RLVI2 controller is shipped configured with DEC standard operating parameters as defined in Table 2-2. MA400250 REY C May 4, 1984 Page 8 PARAMETER SELECTION Control Address 774400 Vector Address 160 Interrupt Vector 4 and 5 Firmware Boot Enabled 22-bit Addressing Disabled TABLE 2-2: FACTORY SET PARAMETERS Most options are etched to the most often used operations. Etches must be cut before alternate jumpers are installed. Several of the options are selectable by using AMP 530153-2 pin jumpers or, alternately, No. 30 wire wrap. Refer to Figure 2-1 for jumper locations. NOTE Certain jumpers are dedicated for factory test only. They must not be altered. 2.3 DEVICE AND VECTOR ADDRESS SELECTION The controller is shipped with DEC standard device and vector addresses preset to 774400 and 160, respectively. Any change in these addresses requires a change in system software. The alternate device and vector addresses are selectable at 776400 a nd 150, respectively. These alternate addresses are typically used for systems with more than two drives where two controllers are required. To configure the second controller for address/vector assignments, cut the etch between WIO and Wll; then jumper W8-W9 and W14-WI5 as shown in Table 2-3. OPTION JUMPERS W1O-11 WB-9 W14-15 Standard Device (774400) IN OUT OUT Standard Vector (160) IN OUT OUT Alternate Device (776400) OUT IN IN Alternate Vector (150) OUT IN IN TABLE 2-3: DEVICE/VECTOR ADDRESS JUMPERS MA400250 REV C May 4, 1984 Page 9 2.4 INTERRUPT REQUEST LEVEL The SDC-RLVI2 interrupts are priority level 4 or 5 as shown in Table 2- 4. Refer to Figure 2-1 for component locations. WI-W2 INTERRUPT REQUEST LEVEL OUT 4 IN 4 AND 5 TABLE 2-4: INTERRUPT REQUEST LEVEL SELECTION 2.5 DRIVE CONFIGURATION Refer to PROM configuration Table 2-5 to determine how to program the configuration PROM for specific drive manufacturer types. The letters in the CONFIGURATION LABEL (right column in Table 2-5) defines the configuration. For example, a PROM labelled D F A B implies that the configuration PROM contents are: 00 50 08 00 84 00 00 84 (IST 8 BYTES) 90 AO 08 00 84 00 00 84 (2ND 8 BYTES) Cl 41 02 00 84 00 00 84 (3RD 8 BYTES) 80 AO 04 00 84 00 00 84 (4TH 8 BYTES). The SDC-RLVI2 supports 5MB RLOI or 1OMB RL02 configured drive types with 40MBs or four logical units maximum capacity. For example, a 5 1/4" Winchester drive, depending on capacity, can be configured as one or more RLOIs or RL02s. When lomega an ALPHA-10.5 drive is used, it should be configured as an RL02 disk drive. Drive configuration is de- termined by W24-W25 jumper; when removed, two like-capacity drives can be used and, when installed, two mixed capacity drives can be used. In the latter case, the drive type (RL01 or RL02) may be different. Example configurations are shown in Figure 2-2. Model Cyl Heads Cap Reduced Start LUN Emulate Config Prom Contents Label Write Cur Precomp Rodime Drives R201 320 2 5.25MB 132(84) 0 (0) I RLOI Cl, 41, 02, 00, 84, 00, 00, 84 A R202 320 4 IOMB 132(84) 0 (0) 2 RLOI 80, AO, 04, 00, 84, 00, 00, 84 B R203 320 2 15.7MB 132(84) 0 (0) 3 RLOI 40, 68, 06, 00, 84, 00, 00, 84 C R204 320 8 21MG 132(84) 0 (0) 4 RLOI 00, 50, 08, 00, 84, 00, 00, 84 D R202 320 4 10.5MB 132(84) 0 (0) I RL02 01, 41, 04, 00, 84, 00, 00, 84 E R204 320 8 21MB 320(84) 0 (0) 2 RL02 90, AO, 08, 00, 84, 00, 00, 84 F Compt Mem Drives CM5410 256 4 8.38MB 256(100) 256(100) 1 RLOI Cl, 00, 04, 01, 00, 01, 00, 84 G CM5616 146 6 12.5MB 256(100) 256(100) 1 RL02 Cl, 00, 06, 01, 00, 01, 00, 84 H CM5412 306 4 10.OMB 256(100) 256(100) 1 RL02 01, 32, 04, 01, 00, 01, 00, 84 1 CM5619 306 6 15.OMB 256(100) 256(100) 3 RLOI 40, 68, 06, 01, 00, 01, 00, 84 J Rotate Mem Drives RMS513 216 6 10.6MB 128(80) 128(80) 1 RL02 DO, D8, 06, 00, 80, 00, 80, 84 K RMS512 216 6 10.6MB 128(80) 128(80) 2 RLOI 80, 6C 06, 00, 80, 00, 80, 84 L RMS518 216 8 14.IMB 128(80) 128(80) 3 RLOI 40, 50, 08, 00, 80, 00 ' 80, 84 M RMS519 306 6 15.04MB 128(80) 128(80) 3 RLOI 40, 68, 06, 00, 80, 00, 80, 84 N Tandon Drives TM603S 153 6 7.52MB 128(80) 153(99) 1 RLOI CO, 99, 06, 00, 80, 00, 80, 84 0 TM602E 230 4 7.53MB 128(80) 128(80) 1 RLOI CO, E6, 04, 00, 80, 00, 80, 84 P TM603E 230 4 7.53MB 128(80) 128(80) 1 RL02 DO, E6, 06 00, 80, 00, 80, 84 Q Seagate Drives ST506 153 4 5.OIMB 128(80) 64(40) 1 RLOI CO, 99, 04, 00, 80, 00, 40, 84 R ST412 306 4 10.OMB 128(80) 64(40) 1 RL02 DI, 32, 04, 00, 80, 00, 40, 84 S Miniscribe Drives MS1006 306 2 5MB 153(99) 0 1 RL01 Cl, 32, 02, 00, 99, 00, 00, 84 T MS1012 306 4 IOMB 153(99) 0 1 RL02 DI, 32, 04, 00, 99, 00, 00, 84 U Olivetti Drive MD571/2 180 4 5.8MB 128(80) 64(40) 1 RLOI CO, 84, 04, 00, 80, 00, 40, 84 V Shugart Drives 604 160 4 5,242,880 128(80) 128(80) 1 RLOI CO, AO, 04, 00, 80, 00, 80, 84 W 606 160 6 7.8MB 128(80) 128(,80) 1 RLOI CO, AO, 06, 00, 80, 00, 80, 84 X 612 306 4 10.OMB 128 128 1 RL02. DI, 32, 04, 00, 80, 00, 80, 84 Y RMS Drives 512 153 8 10.24MB 48 48 2 RLOI 80, 50. 08. 00. 48. 00. 48. 84 Z 512 153 8 10.24MB 4 48 1 RL02 CO, 99, 08, 00, 48, 00, 48, 84 Al TABLE 2-5: DRIVE CONFIGURATION PROM CONTENTS MA400250 REV C May 9, 1984 Page 12 page 12 Type I configurations (like-capacity drives with W24-W25 removed) enable selection of up to four different drive/capacity combinations as stored in the configuration PROM U64. Selection is determined by jumpers W18 through W23 as listed in Table 2-6. JUMPER CONNECTIONS BYTE DEFINITION W18-WI9 and W21-W22 Ist 8 bytes W18-WI9 and W22-W23 2nd 8 bytes W19-W20 and W21-W22 3rd 8 bytes W19-W20 and W22-W23 4th 8 bytes TABLE 2-6: LIKE-CAPACITY DRIVE CONFIGURATIONS JUMPERS Type 11 configurations (mixed capacity drives with W24-W25 installed) enables selection of two drive/capacity combinations as stored in the configuration PROM U56. Selection is determined by jumpers W18 through W20 as listed in Table 2-7. NOTE For mixed capacity drive configurations, jumpers W21, W22 and W23 must be removed. JUMPER CONNECTIONSI BYTE DEFINITION W18-WI9 Ist 8 bytes and 2nd 8 bytes W19-W20 3rd 8 bytes and 4th 8 bytes TABLE 2-7: MIXED CAPACITY DRIVE CONFIGURATION JUMPERS Each separate drive configuration requires 8 bytes of data stored in PROM in order to specify configuration parameters to the S1410 formatter. The controller reads PROM and uses the 8 bytes of data stored to initialize the S1410 and to load the particular Winchester drive configuration parameters. The byte format of the PROM is shown in the following sections. MA400250 REY C May 9, 1984 Page 13 2.5.1 Xebec and Adaptec Byte Format The byte format for Xebec S1410 and Adaptec ACB4000 formatters consists of the eight bytes defined below. BYTE 7 6 5 4 3 2 1 0 0 Bits 7-6 NLU 5 0 4 DT 3-0 HI CYLINDER ADDRESS 1 LOW CYLINDER ADDRESS 2 MAXIMUM NUMBER OF HEADS 3 HIGH WRITE CURRENT ADDRESS 4 LOW WRITE CURRENT ADDRESS BYTE 5 HIGH PRECOMPENSATION ADDRESS 6 LOW PRECOMPENSATION ADDRESS 7 *CONTROL BYTE (xebec only) BYTE 0 parameters are: NLU Number of Logical Units per Drive Bit 7 Bit 6 Logical Units 0 0 4 0 1 3 1 0 2 BIT 5 must be zero. DT= DRIVE TYPE: 0 = RLOI, I = RL02 BYTE 7 See Xebec manual for *control byte bit assignments (Not used for Adaptec) MA400250 REV C May 9, 1984 Page 17 2.5.4 Drive Configuration PROM Examples (Xebec or Adaptec) The PROM type is 74S288, a 32 x 8 bipolar PROM. An example for programming the PROM for the RODIME R0204 for (A) 4 RLOls, and (B) 2 RL02s follows: (A) PROGRAMMING EXAMPLE: RODIME AS 4 RLOIs Byte 0 00 High Cylinder address The R0204 has 321 cylinders (decimal). Mapping the unit to 4 RLOIs results in 321/4 or 80 cylinders/drive. 80 decimal = 50 hex. This is a single byte number; therefore the high byte is 0. Note that 50 hex cyclinders results in formatted capacity of 80 tracks of 32 sectors/track of 256 bytes/sector and 8 tracks/cylinder. 80 x 32 x 256 x 8 = 5.24288 Mbytes. This is the exact capacity of the DEC RLOI. A and B for 4 logical units = 0 C for RLOI = 0. Byte 1 50 Low cylinder address in hex Byte 2 08 Maximum number of heads for R0204 Byte 3 00 Address (high byte) for reduced write current Byte 4 84 Address (low byte) for reduced write current Byte 5 00 Write precomp cylinder address (high byte) Byte 6 00 Write precomp cylinder address (low byte) Byte 7 04 Control byte, 200us pulse/step option. (B) PROGRAMMING EXAMPLE: RODIME AS 2 RL02S Byte 0 90 2 RL02s, high cylinder address = 0 Byte I AO Low cylinder address=321/2=160 decimal=AO hex Byte 2 08 Maximum number of heads for R0204 Byte 3 00 Address (high byte) for reduced write current Byte 4 84 Address (low byte) for reduced write current Byte 5 00 Write precomp cylinder address (high byte) Byte 6 00 Write precomp cylinder address (low byte) Byte 7 04 Control byte, 200us pulse/step option Page 18 has a picture of Xebec S1410 formater cabling. Shows formatter installed in top of disk drive/power supply box. 50 conductor cable from Q-bus to formatter. Red tracer to pin 1 on both boards. Formater has standard MFM cabling, with three connectors: J1 (the wide one) think this is the common data cable J2 the control cable for disk 1, j3 the optional control cable for disk 2 if used. MA400250 REV C May 4, 1984 Page 19 WINCHESTER DRIVES WITH SEPARATE FORMATTER 1. Mount Xebec, OMTI, or Adaptec formatter into the drive mounting bracket. Isolate formatter from mounting bracket with mylar sheet and nylon spacers installed with nylon washers as shown. 2. Secure bracket to both sides of Winchester drive assembly. 3. Connect data cables from formatter module to drive(s). The 20- pin cable plugs into J2 of Xebec/OMTI (JO of Adaptec) formatter for physical drive 1, and J3 (JI) for physical drive 2. Ensure pin I cable orientation is maintained. NOTE When two physical drives are installed, set the first physical drive to respond to unit 0 and the second physical drive to respond to unit I EXCEPT when using OMTI 20C formatter, where the first physcial drive responds to unit I and the second physical drive responds to unit 3. Also, only one drive should be terminated. Remove the drive terminator from the drive physically closest to the formatter. 4. Connect 34-pin cable from formatter edge connector to Winchester drive (physical drive 1), and daisy chain to second drive (drive 2). Ensure correct pin I connections. 5. Connect power cables from power supply to formatter and drive module(s). 6. Connect 50-conductor ribbon cable from SDC-RIV12 to formatter (P2 of Xebec/J4 of OMTI/Adaptec). Ensure pin I connections. 7. Install the SDC-RLVI2 module into the LSI-11 backplane. WINCHESTER DRIVES WITH ON-BOARD FORMATTER If lomega drives are installed refer to lomega manual for cable connec- tions and switch settings. Use the following procedure: 1. Connect the 50-conductor ribbon cable from the SDC-RLVI2 to the lomega host interface. 2. Set the lomega SASI address to respond to address bit 1. 3. Disable SASI bus parity on lomega formatter module. MA400250 REV C May 4, 1984 Page 20 2.7 BOOTSTRAPPING AND 22-BIT ADDRESSING The SOC-RLVI2 has an on-board transparent firmware bootstrap which is initiated when program execution starts at location 773000. It reads two sectors of unit 0, starting from cylinder 0. Sectors 0 and I are loaded into memory starting at location 0. Program execution is then transferred to location 0. Jumper W6-W7 must be installed to enable on-board boot (factory set) and can be disabled by removing W6-W7 if another device has bootstrap precedence. If booting the controller from an external bootstrap, or if 773000 is responded by another device in the system, remove W6-W7. The SDC-RLVI2 can then be booted via ODT as follows: 1. Set the processor to DDT on power-up. 2. Refer to DEC processor manual and ensure proper jumper configuration on the processor module and SDC-RLVI2 module for 18-bit or.22-bit addressing. ---- CPU MODULE---- W5 W6 MODE IN OUT MODE I --------------- SDC-RLVI2 MODULE -------------- JUMPERS ADD BOOT W26-27 W28-29 W28-30 ODT PWR-UP IN OUT IN 22-BIT YES YES OUT OUT IN 18-BIT YES YES OUT IN OUT 18-BIT NO YES 3. While in ODT, enter 774416G. 4. The controller will boot from DLO. 2.8 OFF-LINE CONTROLLER FUNCTION The SDC-RLVI2 microprocessor provides several important off-line functions, which include drive formatting, self-test diagnostics, drive diagnostics, and writing a bad sector file. MA400250 REV C May 9, 1984 Page 21 2.8.1 Drive Formatting The SDC-RLVI2 provides a firmware routine to format attached drive(s). When executed, the format routine formats each track and each cylinder as defined by the SDC-RLVI2 configuration PROM. To format the drive(s), use the following procedure: NOTE: (CR) denotes carriage return 1. While in ODT, access the SOC-RLVI2 disk address register (DAR) at location 774404 by entering 774404/ at the console. The processor will respond with the contents of 774404, displaying 774404/000000 (not necessarily all zeroes). 2. Enter 264 (CR). 3. Access the SDC-RLVI2 control status register (CSR) by entering 774400/. The response will normally be 774400/000201. 4. Enter the appropriate LUN (see Table 2-8). 5. The drive will then be accessed and will format completely. 6. If formatting is unsuccessful, be sure to verify that the configuration PROM is correct for the installed drive. See Section 2.5 for PROM configurations. IOMEGA FORMATTER REMAKE Z-TRACK may destroy customer data on the cartridge. The user should REMAKE Z-TRACK on all lomega disk cartridges before using in the subsystem; otherwise performance will be degraded. For IOMEGA disk drives a firmware routine is provided to perform an IOMEGA command "REMAKE Z-TRACK" to allow the user to change disk cartridge characteristics. The procedure for "REMAKE Z-TRACK" is the same as the formatting pack procedure with the exception of step 2. Enter the appropriate "REMAKE Z-TRACK" code (octal) as follows: 220 - ECC Mode 224 - CRC Mode with Post CRC Check 234 - CRC Mode with No Post CRC Check The sector interleave factor is set to 4 for the above codes. MA400250 REY C May 4, 1984 Page 22 2.8.2 Writing Bad Sector File The SDC-RLY12 includes a firmware program designed to write a bad sector file at the end of each logical drive. The format of the bad sector file is per DEC STD-144, and is compatible with the bad sector file found on the DEC RLOI/RLD2 disk cartridge. DEC diagnostic CZRLM can also be used to generate or check the bad sector file information. To write a bad sector file on each logical unit, while in ODT, deposit 360 into the DAR(774404) and then deposit the appropriate logical unit number (see Table 2-3 in Section 2.8.3) into the CSR (774400). The controller will access the drive and perform the function. 2.8.3 Self-Test The SDC-RLVI2 has an extensive set of diagnostic software built into the controller. Each time a power-up or BINIT routine is completed, the SDC-RLVI2 executes a complete set of self-test diagnostics that test the SDC-RLVI2. Upon successful completion of the self-test diagnostics, LED CR2 is latched in the ON state. If the LED remains OFF after a power-up cycle, part of the subsystem is not functioning properly and the fault should be remedied before trying to use the disk. The diagnostics executed on power-up are: SDC-RLV12 DIAGNOSTICS. These tests check the SDC-RLVI2 microprocessor and buffer memory and all related data paths. If using a new drive, the disk drive must be formatted before any drive tests are attempted. Be sure the controller configuration PROM is cor- rect and configured properly before attempting any drive operations. See Section 2.5 for PROM configurations. In order to execute a function from ODT, open the drive address register (DAR at 774404) and deposit the appropriate command. Then open the control/status register (CSR at 774400) and deposit 4(CR). MA400250 REV C May 9, 1984 Page 23 If the operation is to.be performed on a drive whose logical unit number (LUN) is other than 0, the drive number must be specified as shown in Table 2-8. CSR LUN COMMAND CODE 0 4 1 404 2 1004 3 1404 TABLE 2-8: LOGICAL DRIVE NUMBER (LUN) ERRORS If an error occurs, the SDC-RLVI2 stores the error code in 774414. The error information is an hexadecimal number, whereas the OOT read of the register is octal. Therefore, an octal-to-hexadecimal conversion must be made to obtain the correct error code. The error bit assignments are as follows: Bits 0-3 Hexadecimal Error Code Bits 4,5 Error Class (0-4) Bits 6,7 Ignore ERROR CODES If an error occurs during these tests, the SDC-RLV12 will store the reported error information in location 774414. Errors are of four classes and are defined in Table 2-9. TYPE 0 DISK DRIVE ERRORS TYPE I S1410 FORMATTER ERRORS TYPE 2 COMMAND ERRORS TYPE 3 MISCELLANEOUS MA400250 REV C May 4, 1984 Page 24 TABLE 2-9: ERROR CODE DEFINITIONS HEX DEFINITION TYPE 0 ERROR CODES - DISK DRIVE 0 Controller detected no error during execution of previous operation. I Controller did not detect an index signal from the drive. 2 Controller did not get a Seek Complete signal from the drive after a seek operation. 3 Controller detected a Write Fault from drive during last operation. 4 After controller selected drive, the drive did not respond with Ready signal. 5 Not used. 6 After stepping maximum number of cylinders, controller did not receive Track 00 signal from the drive. 9 Media not loaded. A Insufficient Capacity TYPE I ERROR CODES - CONTROLLER 0 ID Read Error: Controller detected an ECC error in the target ID field on the disk. I Data Error: Controller detected an uncorrectable ECC error in the target sector during a Read operation. 2 Address Mark: Controller did not detect the target address mark (AM) on the disk. 3 Not used. 4 Sector Not Found: Controller found the correct cylinder and track, but not the target sector. 5 Seek Error: Controller detected an incorrect cylinder or track, or both. 6 Not used. 7 Not used. 8 Correctable Data Error: Controller detected a correctable ECC error in the target data field. 9 Bad Track: Controller detected the bad track flag during the last operation. A Interleave Error B Data Transfer not complete. MA400250 REV C May 4, 1984 Page 25 TABLE 2-9: ERROR CODE DEFINITIONS (CONTINUED) TYPE 2 AND 3 ERRORS - COMMAND AND MISCELLANEOUS HEX TYPE DEFINITION 0 2 Invalid Command: Controller has received an invalid command from the host. 1 2 Illegal Disk Address: Controller detected an address that is beyond the maximum range. 0 3 RAM Error: Controller detected a data error during the RAM sector buffer diagnostic. 1 3 Program Memory Checksum Error: During its internal diagnostic, the controller detected a program-memory checksum error. 2 3 ECC Polynominal Error: During the controller internal diagnostic the hardware ECC generator failed its test. For the lomega formatter, this error code indicates parity error on the SASI bus. Table 2-10 is a summary of the error codes returned as the result of Request Sense Status command.. NOTE Address valid bit (bit 7) may or may not be set and is not included here for clarity. MA400250 REV C May 4, 1984 Page 26 TABLE 2-10: ERROR CODE SUMMARY HEX DEFINITION 00 No error detected (command completed OK) 01 No index detected from disk drive. 02 No seek complete from disk drive. 03 Write fault from disk drive. 04 Drive not ready after it was selected. 05 Not used. 06 Track 00 not found. 07-OF Not used. 10 ID field read error. 11 Uncorrectable data error. 12 Address mark not found. 13 Not used. 14 Target sector not found 15 Seek error 16-17 Not used. 18 Correctable data error. 19 Bad track flag detected IA Format error IB-IF Not used. 20 Invalid command 21 Illegal disk address 22-2F Not used 30 RAM diagnostic failure 31 Program memory checksum error. 32 ECC diagnostic failure 33-3F Not used. 2.9 DIAGNOSTIC COMPATIBILITY The SOC-RLVI2 is compatible with the following DEC diagnostic programs: CZRLG Controller Test Part I CZRLH Controller Test Part 2 CZRLK Performance Exercizer DZRLM Bad Sector File Utility Sigma recommends that the SDC-RLVI2 subsystem be excersized using the Performance Exerciser diagnostic as a means of verifying system integ- rity. If problems with the controller or subsystem are suspected, running DZRLG and CZRLH will serve as valuable aids. These diagnostic program are available and may be purhcased from Digitial Equipment Corporation. MA400250 REV C May 4, 1984 Page 27 Section 3 - Programming Considerations 3.1 INTRODUCTION This section describes the function of the bits in each of the five programmable registers, and the commands sent to the CSR for specific disk functions. NOTE To prevent accidental writing on a disk, the SDC- RLVI2 synchronizes on controller ready (CRDY). If the CRDY bit in the CSR changes from clear to set while the processor is in ODT mode, the next read access of any SDC-RLVI2 register produces all zeros. MA400250 REY C May 4, 1984 Page 28 3.2 CONTROL/STATUS REGISTER (CSR) The control/status register is a 16-bit word-addressable register with standard address of 774400 for 18-bit addressing, an 17774400 for 22- bit addressing. Bits I through 9 can be read or written; the other bits can only be read. The it functions are described below. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERR DE E3 E2 El E0 DS1 DSO C IE BA BA F2 Fl FO D RDY 17 16 RDY READ ONLY READ/WRITE READ ONLY DRDY DRIVE READY. When set, this bit indicates that the selected drive is ready to receive a command or supply valid read data. Cleared when a Seek or head select operation is started; set when the Seek operation is completed. F2-FO FUNCTION CODE. These bits are the function code set by software ware to indicate the command to be executed. FUNCTION COMMAND OCTAL F2 Fl FO CODE 0 0 0 Maintenance mode (NOP) 0 0 0 1 Write Check I 0 1 0 Get Status 2 0 1 1 Seek 3 I 0 0 Read Header 4 1 0 1 Write Data 5 1 1 0 Read Data 6 1 1 1 Read Data without 7 Header Check Command execution starts when CRDY (bit 7) is cleared by software. The commands are described in detail in Section 3-7. The function code is cleared by initializing bus (BINIT L). BA17, EXTENDED ADDRESS BITS. These two bits are the upper-order bus BA16 address bits for 18-bit buses. They are read and written as bits 4 and 5 of the CSR and function as address bits 16 and 17 of the BAR. Writing bits 4 and 5 of the CSR also writes bits 0 and 1 of the BAE. MA400250 REY C May 4, 1984 Page 29 IE INTERRUPT ENABLE. When CRDY is asserted bit 6 allows the controller to interrupt the processor. This interrupt occurs at the termination of a command. Once an interrupt request is placed on the LSI-11 bus, it is not removed until acknowledged by the LSI-11 processor even if IE (bit 6) is cleared. Cleared by initializing the bus. CRDY CONTROLLER READY. When cleared by software, this bit indicates that the command in bits 1-3 is to be executed. Set by the controller at completion of a command, at detection of an error, or by initializing the bus. Software cannot set this bit because no registers are accessible while CRDY is 0. DSO, DRIVE SELECT. These bits determine which drive will DS1 communication with the controller via the drive bus. Cleared by initializing the bus. E3-EO CONTROLLER STATUS ERRORS. These bits are the error code set by the controller to indicate one of the folIowing errors: --ERROR CODE-- ERROR OCTAL E3 E2 El EO CODE* 0 0 0 1 Operation incomplete (OPI) 1 0 0 1 0 Data CRC (DCRC) 2 0 0 1 1 Header CRC (HCRC) 3 0 1 0 0 Data late (DLT) 4 0 1 0 1 Header not found (HNF) 5 1 0 0 0 Nonexistent memory (NXM) 10 I 0 0 1 Parity error abort (PAR ERR) 11 *See Section 3-7. Operation incomplete indicates that the current command was not completed within the OPI timeout period of 550ms. A data CRC error indicates that, while ready the data field from the disk, an error was found. A header CRC error indicates that, while reading the header from the disk, an error was found. The CRC check is performed on the first and second header words, although the second header word is always 0. MA400250 REV C May 4, 1984 Page 30 Data late indicates that the FIFO RAM was more than half full and the controller was not able to read the next sequential sector. This error may occur during a Read without Header Check command. Header not found indicates that OPI timeout occurred while the controller was searching for the correct sector to read or write. A header compare did not occur. A nonexistent memory error indicates that, during a DMA transfer, the memory location addressed did not respond with RPLY within IOUs. A memory parity error abort indicates that a parity error was detected while reading the system optional memory that has parity error checking. If an error was detected, the current command to the SDC-RLVI2 is aborted. DE DRIVE ERROR. This bit is buffered from the drive error inter- face line. When set, it indicates that the selected drive has flagged an error, the source of which can be determined by executing a Get Status command. DE will not set ERR or CRDY until the usual occurrence of CRDY. ERR COMPOSITE ERROR. When set, this bit indicates that one or more of the error bits (bits 10-14) are set. When an error occurs, the current operation terminates and an interrupt routine is started if the interrupt enable bit (bit 6 of the CSR) is set. All error bits are cleared by initializing the bus by starting a new command, with the exception of DE an ERR if they were caused by a drive error. When the LSI-11 bus is initialized with BINIT L, bits 1-6 and 8-13 are cleared, and bit 7 (CRDY) is set. Bit 0 (DRDY) is set when the selected drive is ready to accept a command; otherwise, this bit is cleared. Bit 14(DE) is clear as long as there is no drive error. Otherwise, this bit is set and stays set until the drive error is corrected; or if bit 3 (drive reset) is set in the DAR and the controller is sent a Get Status command, the DE bit is cleared. Bit 15 (ERR) is set when there is a drive or controller error in bits 10-14. At the beginning of each controller command, error bits 10-13 are automatically cleared. At the completion of each controller command, it 7 is automatically set. Bit 7 is also set if an error is detected during command execution. MA400250 REY C May 4, 1984 Page 31 3.3 BUS ADDRESS REGISTER (BAR) The bus address register is a 16-bit, word addressable register with a standard address of 774402 for 18-bit addressing, an 17774400 for 22- bit addressing. Bits 9 through 15 can be read or written; bit 0 is usually written as 0. The bus address register indicates the memory location for the DMA data transfer during a read or write operation. The register contents are automatically incremented by 2 as each word is transferred between system memory and controller. BAR is cleared by initializing the bus (BINIT L). The bus address can be expanded for an 18-bit LSI-11 bus by using bits 4 and 5 (BA16 and BA17) of the CSR, or by using bits 0 and I of the BAE register. The bus address can be expanded for a 22-bit LSI-11 bus by using the BAE register (BAE16-BAE21). NOTE When using 22-bit mode, writing CSR bits 4 and 5 modifies BAE bits 0 and I - and vice versa. 3.4 DISK ADDRESS REGISTER (DAR) The disk address register is a 16-bit, read/write, word addressable register with a standard address of 774404 for 18-bit addressing, and 17774404 for 22-bit addressing. Its contents has one of three meanings, depending on the command being performed. DAR is cleared by initializing the bus (BINIT L). COMMAND BAR FUNCTION Seek Head selected, number of cylinder to move, direction Read Data or Head selected, cylinder address, Write Data sector address Get Status Send drive status to MPR; reset error registers MA400250 REV C May 4, 1984 Page 32 3.4.1 DAR During a Seek Command To perform a Seek command, the program must provide the head selected (HS), direction to move (DIR), and the cylinder address difference (OF). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DF8 DF7 DF6 DFSDF4 DF3 DF2 DFI DFO 0 0 HS O DIR O MRKR MRKR MARKER. Must be 1. BIT 1 Must be 1, indicating to the drive that a Seek command is being issued and that the other bits in the register hold the Seek specifications. DIR DIRECTION. This bit indicates the direction in which the Seek is to take place. When set, the heads move toward the spindle (to a higher cylinder address). When cleared, the heads move away from the spindle (to a lower cylinder address). The actual distance moved depends on the cylinder address difference (bits 7-15). BIT 3 Must be 0. HS HEAD SELECT. Indicates which head (disk surface) is to be selected: 1 = lower, 0 = upper. BITS 5,6 Reserved OF CYLINDER ADDRESS DIFFERENCE. Indicates the number of cylinders the heads are to move on a Seek. MA400250 REV C May 4, 1984 Page 33 3.4.2 DAR During a Read, Write, or Write Check Command For a Read, Write, or Write Check command, the DAR provides the head selected (HS) and the address of the first sector to be transferred (SA). As each sector is transferred, the DAR sector address increments by 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CA8 CA7 CA6 CAS CA4 CA3 CA2 CA1 CAO HS SA5 SA4 SA3 SA2 SAI SAO SA SECTOR ADDRESS. Address of one of the 40 sectors on a track Octal range is 0 to 47. HS HEAD SELECT. Indicates which head (disk surface) is to be selected: 1 = lower, 0 = upper. CA CYLINDER ADDRESS. Address of one of the 256 cylinders for RLO1;or 512 cylinders for RL02. Octal range 0 to 777. DAR DURING A GET STATUS COMMAND 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (bits 15 - 8 not used) 0 0 0 0 RST 0 GS MRKR MRKR MARKER. Must be 1. GS GET STATUS. Must be 1, indicating to the drive to send its status word. At the completion of the Get Status command, the drive status word is read into the controller multipurpose register (MPR). With this bit set, bits 8-15 are ignored by the drive. BIT 2 Must be 0. RST RESET. When set, the disk drive clears its error register of soft errors before sending a status word to the controller. BITS 4-7 Must be Os. BITS 8-15 Not used. MA400250 REY C May 4, 1984 Page 34 3.5 MULTIPURPOSE REGISTER (MPR) The multipurpose register is a 16-bit, read/write, word- addressable register. It is accessed using the standard address of 774406 for 18- bit addressing, and 17774404 for 22-bit addressing. Following a Read Header command or a Get Status command, reading the MPR obtains sector header or drive status information. Writing to the MPR is used to set the word count. The word count is cleared by initializing the bus (BINIT L). 3.5.1 Writing the MPR to Set The Word Count Before starting a DMA transfer, the MPR is loaded with the word count. The program must load the MPR with the 2's complement of the number of words to be transferred. The MPR is written in the format shown and described below. As each word is transferred, the MPR is automatically incremented by 1. The reading or writing operation continues until a word count overflow occurs, indicating that all words have been trans- ferred. The word count can range from I to 2120 data words. The maximum word count is limited by the maximum number of sectors available (40) and the maximum words per sector (128). NOTE Once written, the word count cannot be read back. Reading the MPR does not change the word count. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 WC12 - - - WC0 WC WORD COUNT. This is the 2's complement of the total number of words to be transferred. BITS 13-15 Must be all Is for word count to be in correct range. MA400250 REV C May 9, 1984 Page 35 3.5.2 Reading The MPR after A Read Header Command 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CA8 - CAO HS SA5 - SAO FIRST WORD SECOND WORD: all zeros THIRD WORD: 16 bit CRC 3.5.3 Reading the MPR after a Get Status Command 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDE HCE WL SKTO 0 WGE VC 0 DT HS 0 1 1 STATE STATE STATE. Defines the state of the drive as follows: Bit 2 Bit I Bit 0 State of Drive 0 0 0 Load State 1 0 1 Seek linear mode (lock on) Values not given are not used. BIT 3 Will always be 1. BIT 4 Will always be 1. BIT 5 Will always be 0. HS HEAD SELECT. Indicates head selected: 1 lower, 0 = upper. DT DRIVE TYPE. Indicates type of drive: 0 RLOI, 1 RL02. BIT 8 Will always be 0. MA400250 REY C May 9, 1984 Page 36 vc VOLUME CHECK. Set every time the drive goes into load heads state. This asserts a drive error at the controller, but not on the front panel. VC is an indication that the program does not know which disk is present until it has read the serial number and bad sector file. (The disk might have been changed while the heads were unloaded.) WGE WRITE GATE ERROR. Indicates that the write gate was asserted when the drive was not ready, the sector pulse was asserted, or the drive was write-locked. BIT 11 Must always be 0. SKTO SEEK TIME OUT. Indicates the heads did not come on track within a specific time during a Seek command. WL WRITE LOCK. Indicates write lock status of selected drive: 0 unlocked, I = protected. HCE HEAD CURRENT ERROR. Indicates write current was detected in the heads when write gate was not asserted. WOE WRITE DATA ERROR. Indicates write gate was asserted, but no pulses were detected on the write data line. 3.6 BUS ADDRESS EXTENSION REGISTER (BAE) The bus address extension register is a 6-bit read/write register used to drive address bits 16-21 for a 22-bit LSI-11 bus. The BAE has a standard address of 17774410 for 22-bit addresssing. A write to the BAE loads TS DAL 0-5 into BAE 0-5, shown below. Reading the BAE enables bank select 7 (BBS7 L) to the LSI-11 bus. When address bits 13-21 are all Is, the SDC- RLVI2 drives BBS7 L to direct data to the 1/0 page. The two least significant bits of the BAE (bus address lines 16 and 17) are mirrored in bits 4 and 5 of the CSR. The same bits can be read or written as CSR bits 4 and 5, or BAE bits 0 and 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 BA21 - BA16 MA400250 REY C May 9, 1984 Page 37 3.7 CSR COMMANDS This section describes the commands sent to the control/status register (CSR), bit FO, Fl, and F2, to perform a specific disk function. A prere- quisite to issuing any command is that CRDY (controller ready) is set in the CSR. Software cannot set this bit and cannot access any register if bit 7 = 0. At the start of each new command, the error bits in the CSR (bits 10-13) are automatically cleared. At the completion of each command, the CRDY bit is automatically set. CROY is also set if an error is detected during command execution. The commands are define in detail below where the number in parentheses after each command is the octal code for the command. WRITE CHECK (1) PREREQUISITE: The disk heads must be placed at the correct track by issuing a Seek command if necessary. BAR must be loaded with the address of the first location of the data block in system memory. The word count of the data block length must be loaded in the MPR and the DAR must be loaded with the starting disk address location. The Write Check command is used to verify that data was written on the disk correctly. It is used after writing a block of data on the disk by the Write Data command. The Write Check command reads this same block of data and compares it with the data in the computer's system memory. This comparison is performed in the controller, thus the source data must be transferred out of memory into the controller FIFO buffer. A bit-by-bit comparison of the header on the disk and the contents of the disk address register checks for a header match. Once a header match is found and the header CRC validates the match, the 128 words of data are read from the disk. This data is then compared with the serial data coming out of the FIFO serializer (SER DATA OUT). A compare error or a data CRC error sets bit 11 in the CSR. NOTE When writing only a partial sector (less than 128 words), words with all Os are used to fill the remaining portion of the sector. MA400250 REV C May 9, 1984 Page 38 GET STATUS (2) PREREQUISITE: The software must first verify that the controller ready bit is set. (The drive does not have to be ready.) Then a status request word must he loaded into the DAR where bits 0 and 1 must be set; bit 3 (reset) can be either 0 or 1, and all other bits must be Os. (See Paragraph 3.4.) A Get Status command in the CSR asks the selected disk drive to return information about its current operation and error status. If DAR reset bit (bit 3) is set, the disk drive first clears its error register of all soft errors before sending back the drive status. When the drive sends back its status word, it is stored in the FIFO buffer and can be accessed by reading the MPR. DRDY (drive ready) does not have to be set to issue a Get Status command. For example, a Get Status command can be issued during a seek operation or when the drive is in its load state. SEEK (3) PREREQUISITE: The present location of the disk head must he known. This can be determined with a Read Header command. Then the software must compute the cylinder address difference (DF) needed by the drive to move the heads to the new location. Then the DAR must be loaded with the head positioning information. The DAR must include the number of cylinders to move (bits 7-15), the head select bit (bit 4), and the direction to move (bit 2). Bits 6, 5, and I must be set to 0; bit 0 must be set to 1. The Seek command shifts the contents of the DAR to the disk drive. The DAR contains the head selected for the next data transaction, the cylinder difference address, and the direction of movements once the drive receives this head positioning information, it moves the head to the new track location. MA400250 REV C May 9, 1984 Page 39 READ HEADER (4) PREREQUISITE: A Get Status command must be issued and DRDY must be set in the CSR. The Read Header command reads the first header found on the selected drive and stores the three header words in the FIFO RAM. The first word, WDI, includes the cylinder address, the head selected, and the sector address. The second word, WD2, is all zeros. The third word, W03, has the header CRC information. These words can be read from the FIFO RAM buffer by consecutive read MPR instructions. Three read MPR instructions are needed to read three FIFO words. Reading the first header word provides enough head positioning information to permit softweare computation of the cylinder difference for another Seek command to a new track address. WRITE DATA (5) PREREQUISITE: The head must be loaded at the correct track by issuing a Seek command if necessary. The 2's complement of the words to be written (word count) must be loaded into the MPR. The Write Data command enables the controller DMA circuitry. The SDC-RLV12 becomes LSI-11 bus master, and data words are loaded into the FIFO buffer. When the drive is ready, header information is read from the disk and compared with the first sector address stored in the DAR. Once a header match is found, the FIFO data is written on the disk in sequential sectors until the word count is complete. The BAR and word count are incremented for each word transferred. If only part of a sector is filled by the new data, the rest of the sector area is filled with Os. At the end of the sector, the sector part of the DAR is incremented. At the end of a transfer, CRDY is set and an interrupt is made if IE is set. MA400250 REY C May 9, 1984 Page 40 READ DATA (6) PREREQUISITE: The head must be loaded at the correct track by issuing a Seek command if necessary. The 2's complement of the words to be read (word count) must be loaded into the MPR. The Read Data command causes headers to be read from the disk and compared to the sector address stored in the DAR. When a header match is found, disk data words are transferred into the FIFO memory. Both the BAR and word count are incremented for each word transferred. After four words are read from the disk, the microsequencer starts a DMA transfer on the LSI-11 bus. The data transfer ends when the word counter overflows. If the word count is not complete, the next sector is read. Otherwise, CRDY is set and an interrupt is made if IE is set. READ WITHOUT HEADER CHECK (7) PREREQUISITE: The location of the sector with the bad header must be known. The BAR must be loaded with the starting memory location to place the words to be read. The MPR must be loaded with the word count in 2's complement form. The Read without Header Check allows the recovery of data if the headers cannot be read. If header not found (HNF) or header CRC (HCRC) errors are found on a sector, then data cannot be recovered by the usual Read Data command. A Seek command must be issued to position the head on the sector with the bad header. Then the sector preceding the bad sector must be found by performing consecutive Read Header commands. Finally, a Read without Header Check command must be issued within 300us to recover the data in the bad sector. The BAR and word count are incremented for each word transferred. Data CRC is checked at the end of a sector. If the word count is not complete, the next sector is read. Otherwise, CROY is set and an interrupt is made if IE is set. NOTE The DAR is automatically incremented after each sector is transferred. MA400250 REY C May 9, 1984 Page 41 3.8 PROGRAMflING EXAMPLES The following example show the use of SOC-RLVI2 commands in software programs. SEEK OPERATION 1. Issue a Read Header command to the desired disk drive and wait for an interrupt request or wait for CRDY. 2. Check error flag in CSR. 3. Read the header word from MPR. 4. Computer the difference address and the direction for the seek. 5. Write the difference word into DAR. 6. Issue the Seek command to the drive and wait for seek to be completed as indicated by DRDY. 7. Check error flag in CSR. Steps 1, 2 and 3 above are not needed for the next Seek commands if the software program keeps the current cylinder address and head selected in memory. Reading sequential headers gives head position and present direction so the program can optimize the shortest distance to the new location. MA400250 REY C May 9, 1984 Page 42 DATA TRANSFER OPERATION 1. Perform the steps of the seek operation described above. 2. Write the extended bus address in BAE if using 22-bit addressing. 4. Write DAR with the cylinder address, head selection, and sector address of the first disk location to be transferred. 5. Load MPR with the word count (2's complement of words to be transferred). 6. Issue a Read Data, Write Data, or Write Check command in CSR. 7. Wait for interrupt or test for CRDY. 8. Check CSR for error flag. Seek commands or data transfer commands may be given to other drives between issuing a Seek to the first drive and issuing a data transfer command. As soon as a Seek command is issued to the first drive, it returns an interrupt and sets CRDY. A Seek command may be given to another drive while the first drive is seeking. No interrupts occur when all the seeks are complete, so as soon as all Seek commands are issued, data transfer commands may be issued. Starting with the drive that was given the shortest seek distance makes it possible for the drive that completes its seek first to immediately perform its data transfer and interrupts when done.